Design through Verilog HDL (Record no. 116415)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00524nam a22002057a 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 260428b |||||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9788126519316 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.3815 PAD |
| 100 ## - MAIN ENTRY--AUTHOR NAME | |
| Personal name | Padmanabhan T.R. |
| 245 ## - TITLE STATEMENT | |
| Title | Design through Verilog HDL |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication | New Delhi |
| Name of publisher | Wiley |
| Year of publication | 2009 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | 455p. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Design |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Verilog |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | HDL |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) | |
| Subject | Electronics and Communication Engineering |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Sundari B.Bala Tripura |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | General Book |
| Withdrawn status | Lost status | Damaged status | Not for loan | Home library | Current library | Full call number | Accession Number | Koha item type | Exchange Rate | Department |
|---|---|---|---|---|---|---|---|---|---|---|
| Central Library CUK | Central Library CUK | 621.3815 PAD | 49742 | General Book | 1 | Electronics and Communication Engineering |